Non-volatile semiconductor memory cells employing floating gates which are completely surrounded by an insulative layer such as silicon dioxide are well-known in the prior art. Typically, a polycrystalline silicon (polysilicon) layer is used to form the floating gates. Charge is transferred to the floating gates through a variety of mechanisms such as avalanche injection, channel injection, tunnelling, etc.
The charge on the floating gate affects the surface channel conductivity in the cell. If the conductivity is above a certain level, the cell is deemed to be programmed in one binary state, and if the conductivity is below another level it is deemed to be programmed in the opposite binary state. These cells are referred to in the prior art as EPROMs, EEPROMs, flash EPROMs and flash EEPROMs.
In general, an EPROM or an EEPROM comprises a silicon substrate including source and drain regions which define a channel therebetween. Disposed above the channel is a polysilicon floating gate. The floating gate separated from the substrate by a relatively thin gate insulative layer. A control gate is disposed above, and insulated from, the floating gate. The control gate is also commonly fabricated of polysilicon. An example of this category of device is shown in U.S. Pat. Nos. 3,500,142 and in U.S. Pat. No. 4,203,158.
In the case of a flash EEPROM cell, electrons (i.e., charge) are stored on the floating gate in a capacitive manner. For these devices the memory cell comprises only a single device and the entire memory array is erased at one time. That is, individual cells or groups of cells are not separately erasable as in current EEPROMs. A flash EEPROM or flash EPROM device is disclosed in co-pending application Ser. No. 07/253,775, filed Oct. 5, 1988, entitled, "Low Voltage EEPROM Cell", assigned to the assignee of the present invention. U.S. Pat. No. 4,698,787 of Mukherjee et al., also discloses an electrically erasable programmable memory device which is programmed by hot-electron injection from the channel onto the floating gate and erased by Fowler-Nordheim tunnelling from the floating gate to the substrate.
Recently, much attention has been focused on contactless, electrically programmable and electrically erasable memory cell arrays of the flash EEPROM variety. In the contactless array, cells employ elongated source/drain regions which are sometimes referred to as "buried bit lines". These cells often require virtual ground circuitry for sensing and programming. An example of this type of array and a process for fabricating the same is disclosed in U.S. Pat. No. 4,780,424, which application is assigned to the assignee of the present invention. In certain instances, the drain regions are shallow compared to the source regions, while the source regions have more graded junctions. The floating gates are formed over a tunnel oxide disposed between the source and drain regions. Word lines are generally disposed perpendicular to the source and drain regions.
The principle upon which these EEPROM cells operate is that electrons (i.e., charge) are stored on the floating gate in a capacitive manner. By way of example, during programming of an EEPROM device, the control gate is usually taken to a high positive potential ranging between 12 and 20 volts. The source is grounded and the drain is taken to an intermediate potential of approximately 7 volts. This creates a high lateral electrical field within the channel region nearest to the drain. The high lateral electric field accelerates electrons along the channel region to the point where they become "hot". These hot-electrons create additional electron-hole pairs through impact ionization. A large number of these electrons are attracted to the floating gate by the large positive potential on the control gate.
During erasing of an EPROM device, the control gate is usually grounded and the drain is left unconnected. The source is taken to a high positive potential, creating a high vertical electric field from the source to the control gate. Charge is erased from the floating gate by the mechanism of Fowler-Nordheim tunnelling of electrons through the gate oxide region between the source and the floating gate in the presence of such a field.
One problem associated with prior art memory cells is that after the floating gate has been repeatedly erased the device can function as a depletion-mode device in which current flows when the threshold of the memory cell is below the gate bias during read operation. In other words, frequent erasing of the gate results in a lowered (i.e., negative) voltage threshold. The presence of a negative threshold voltage is problematic in that it can completely disable an entire column line within an array.
To combat this problem several prior art cells have incorporated select transistors into the basic memory cell design for the purpose of inhibiting current flow between the source and drain regions after the floating gate has been repeatedly erased. These designs inhibit current flow between source and drain in the over erased memory cell during read conditions. Thus, even if the floating gate is repeatedly erased, becoming and acting like a depletion-mode device, no current will flow. Such an EEPROM cell is shown in co-pending U.S. patent application entitled, "EEPROM Cell with Integral Select Transistor", filed 2/2/87; Ser. No. 07/009,998; which is assigned to the assignee of the present invention. Other memory cells incorporating a select gate architecture are disclosed in U.S. Pat. Nos. 4,087,795; 4,412,311; 4,590,503; 4,328,565; 4,622,656; and 4,258,378.
As will be seen, the present invention comprises an electrically erasable and electrically programmable memory cell with an integral select transistor. The select transistor is fabricated along a vertical dimension of the channel region to achieve a minimal area two-transistor memory cell. According to the present invention the achievable cell density is more than double that of prior art memory arrays.